Tick to Trade in Under 6 Microseconds
Kernel-bypass networking, CPU pinning, NUMA-aware memory allocation, and co-location at Equinix NY4 and NY5. The full infrastructure stack optimized for the lowest measurable latency.
Published Performance Numbers
Measured at NY4, standard 10GbE cross-connect, market-open load conditions. Methodology detailed in our technical documentation.
How We Measure Tick to Trade
Tick-to-trade latency is the elapsed time from the moment a market data packet is received at the NIC to the moment an outbound order packet leaves the NIC. It encompasses the full software stack: kernel bypass driver, feed handler normalization, strategy signal computation, risk check, order router scoring, and gateway wire format encoding.
Hardware timestamps are taken at the NIC using PTP-synchronized clocks. Measurements are collected over a 90-minute window during market open. P50 and P99 are computed across all symbols and order types in the session window.
- NIC-to-NIC hardware timestamping
- PTP clock synchronization, drift under 10 ns
- Tested under representative open-auction load
- Both P50 and P99 reported, not just best-case
- Results reproducible on standard co-lo hardware
| Component | Latency |
|---|---|
| Kernel bypass + NIC receive | 80 ns |
| Feed handler normalization | 180 ns |
| Signal computation | 1.2 us |
| Risk check | 220 ns |
| AI routing decision | 6 us |
| Gateway encode + NIC send | 340 ns |
Stack Optimizations That Deliver This
Kernel Bypass Networking
DPDK-based packet I/O removes the OS kernel from the data path. Packets go directly from NIC to the feed handler user-space buffer with no system call overhead.
CPU Pinning and NUMA Isolation
Hot threads are pinned to isolated CPUs. Memory is allocated on the same NUMA node as the NIC. No cross-socket traffic on the critical path. CPU frequency scaling disabled.
Equinix NY4 and NY5 Co-Location
Physical hardware installed in the same cage row as major exchange matching engines. Cross-connect on 10GbE direct fiber. No routing hops between EurekaLabs hardware and the exchange.
FPGA Pre-Processing
Time-sensitive feed formats are decoded on the FPGA card before hitting the CPU. The CPU receives already-decoded normalized events rather than raw packet bytes.
PTP Hardware Timestamping
All latency measurements use PTP-synchronized hardware timestamps at the NIC. Clock drift is maintained under 10 nanoseconds, so published numbers reflect real elapsed time.
Continuous Latency Monitoring
Latency percentiles are computed continuously and exposed via the management API. Clients can monitor their own tick-to-trade numbers in real time and receive alerts on p99 spikes.
Measure Your Own Tick-to-Trade Numbers
We provide a benchmarking harness that runs against your strategy code in our environment. You see the exact numbers before committing to deployment.